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MIL-STD-1750A or 1750A is the formal definition of a 16-bit computer instruction set architecture (ISA), including both required and optional components, as described by the military standard document MIL-STD-1750A (1980). In addition to the core ISA, the definition defines optional instructions, such as a FPU and MMU. Importantly, the standard does not define the implementation details of a 1750A processor. == Internals == The 1750A supports 216 16-bit words of memory for the core standard. The standard defines an optional memory management unit that allows 220 16-bit words of memory using 512 page mapping registers (in the I/O space), defining separate instruction and data spaces, and keyed memory access control. Most instructions are 16 bits, although some have a 16-bit extension. The standard computer has 16 general purpose 16-bit registers (0 through 15). Registers 1 through 15 can be used as index registers. Registers 12 through 15 can be used as base registers. Any of the 16 registers could be used as a stack pointer for the SJS and URS instructions (''stack jump subroutine'' and ''unstack return subroutine''), but only register 15 was used as the stack pointer for the PSHM and POPM instructions (''push multiple'' and ''pop multiple''). The computer has instructions for 16, and 32-bit binary arithmetic, as well as 32 and 48 bit floating point. I/O is generally via the I/O instructions (XIO and VIO), which have a separate 216 16-bit word address space and may have a specialized bus. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「MIL-STD-1750A」の詳細全文を読む スポンサード リンク
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