|
The Intel Pentium microprocessor was introduced on March 22, 1993. Its microarchitecture, dubbed P5, was Intel's fifth-generation and first superscalar IA-32 microarchitecture. As a direct extension of the 80486 architecture, it included dual integer pipelines, a faster floating-point unit, wider data bus, separate code and data caches and features for further reduced address calculation latency. In 1996, the ''Pentium with MMX Technology'' (often simply referred to as ''Pentium MMX'') was introduced with the same basic microarchitecture complemented with an MMX instruction set, larger caches, and some other enhancements. The P5 Pentium competitors included the Motorola 68060 and the PowerPC 601 as well as the SPARC, MIPS, and Alpha microprocessor families, most of which also used a superscalar in-order dual instruction pipeline configuration at some time. Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core (P54C), augmented by multithreading, 64-bit instructions, and a 16-wide vector processing unit.〔§3 of 〕 Intel's low-powered Bonnell microarchitecture employed in Atom processor cores also uses an in-order dual pipeline similar to P5. ==Development== The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486.〔p. 1, ''The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips'', Robert P. Colwell, Wiley, 2006, ISBN 978-0-471-73617-2.〕 Design work started in 1989;〔p. 88, "Inside Intel", ''Business Week'', #3268, June 1, 1992.〕 the team decided to use a superscalar architecture, with on-chip cache, floating-point, and branch prediction. The preliminary design was first successfully simulated in 1990, followed by the laying-out of the design. By this time, the team had several dozen engineers. The design was taped out, or transferred to silicon, in April 1992, at which point beta-testing began.〔("The hot new star of microchips" ), Monica Horten, ''New Scientist'', #1871, pp. 31 ff., May 1, 1993. Accessed on line June 9, 2009.〕 By mid-1992, the P5 team had 200 engineers.〔p. 89, "Inside Intel", ''Business Week'', #3268, June 1, 1992.〕 Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, and to formally announce the processor in September 1992,〔p. 8, "Intel to offer a peek at its `586' chip", Tom Quinlan, ''InfoWorld'', March 16, 1992.〕 but design problems forced the demo to be cancelled, and the official introduction of the chip was delayed until the spring of 1993.〔p. 1, "Design woes force Intel to cancel 586 chip demo", Tom Quinlan and Cate Corcoran, ''InfoWorld'' 14, #24, June 15, 1992.〕〔pp. 1, 103, "P5 chip delay won't alter rivals' plans", Tom Quinlan, ''InfoWorld'' 14, #30, July 27, 1992.〕 John H. Crawford, chief architect of the original 386, co-managed the design of the P5,〔p. 54, "Intel Turns 35: Now What?", David L. Margulius, ''InfoWorld'', July 21, 2003, ISSN 0199-6649.〕 along with Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU.〔p. 21, "(Architecture of the Pentium microprocessor )", D. Alpert and D. Avnon, ''IEEE Micro'', 13, #3 (June 1993), pp. 11–21, .〕 Vinod K. Dham was general manager of the P5 group.〔p. 90, "Inside Intel", ''Business Week'', #3268, June 1, 1992.〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「P5 (microarchitecture)」の詳細全文を読む スポンサード リンク
|