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Intel 8237 is a direct memory access (DMA) controller, a part of the MCS 85 microprocessor family. It enables data transfer between memory and the I/O with reduced load on the system's main processor by providing the memory with control signals and memory address information during the DMA transfer. The 8237 is a four-channel device that can be expanded to include any number of DMA channel inputs. The 8237 is capable of DMA transfers at rates of up to per second. Each channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k bytes with a single programming.〔Intel microprocessors by Barry B Brey〕 A single 8237 was used as the DMA controller in the original IBM PC and IBM XT. The IBM PC AT added another 8237 in master-slave configuration, increasing the number of DMA channels from four to seven. Later IBM-compatible personal computers may have chip sets that emulate the functions of the 8237 for backward compatibility. ==Modes== The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used: * Single - One DMA cycle, one CPU cycle interleaved until address counter reaches zero.〔 * Block - Transfer progresses until the word count reaches zero or the EOP signal goes active.〔 * Demand - Transfers continue until TC or EOP goes active or DRQ goes inactive. The CPU is permitted to use the bus when no transfer is requested.〔 * Cascade - Used to cascade additional DMA controllers. DREQ and DACK is matched with HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals is executed by cascaded chip.〔 Memory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.〔(aluzina.org - Intel 8237/8237-2 High performance. Programmable DMA controller ) (.pdf) datasheet〕 In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It is used to repeat the last transfer.〔 The terminal count (TC) signals end of transfer to ISA cards. At the end of transfer an auto initialize will occur configured to do so. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Intel 8237」の詳細全文を読む スポンサード リンク
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