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AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and scheduled to be supported in 2015 with Intel's Knights Landing processor. AVX-512 is the latest ISA based on Intel's Larrabee project, but while related to, it is not compatible with the earlier 512-bit AVX-like vector instructions sets in the Xeon Phi line of processors. AVX-512 consists of multiple extensions not all meant to be supported by all processors implementing them. Only the core extension AVX-512F (AVX-512 Foundation) is required by all implementations. == Instruction set== The AVX512 instruction set consists of several separate sets each having their own unique CPUID feature bit, however they are typically grouped by supporting processor generation. ;AVX-512F, AVX-512 CDI, AVX-512 ERI, AVX-512 PFI: Introduced with Xeon Phi Knights Landing and Skylake Xeon, with the last two (ERI and PFI) being specific to Knights Landing. * ''AVX-512 Foundation'' expands most 32-bit and 64-bit based AVX instructions with EVEX coding scheme to support 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control, supported by Knights Landing and Skylake Xeon * ''AVX-512 Conflict Detection Instructions (CDI)'' efficient conflict detection to allow more loops to be vectorized, supported by Knights Landing〔 and Skylake Xeon * ''AVX-512 Exponential and Reciprocal Instructions (ERI)'' exponential and reciprocal operations designed to help implement transcendental operations, supported by Knights Landing〔 * ''AVX-512 Prefetch Instructions (PFI)'' new prefetch capabilities, supported by Knights Landing〔 ;AVX-512 BW, AVX-512 DQ, AVX-512 VL: Introduced with Skylake Xeon. * ''AVX-512 Byte and Word Instructions (BW)'' extends AVX-512 to cover 8-bit and 16-bit integer operations * ''AVX-512 Doubleword and Quadword Instructions (DQ)'' adds new 32-bit and 64-bit AVX-512 instructions〔 * ''AVX-512 Vector Length Extensions (VL)'' extends most AVX-512 operations to also operate on XMM (128-bit) and YMM (256-bit) registers〔 ;AVX-512 IFMA52, AVX-512 VBMI: Future extensions scheduled for Cannonlake.〔(【引用サイトリンク】title=Intel ‘Skylake’ processors for PCs will not support AVX-512 instructions )〕 * ''AVX-512 Integer Fused Multiply Add (IFMA52). Fused multiply add for 52-bit integers. * ''AVX-512 Vector Byte Manipulation Instructions (VBMI)'' adds vector byte permutation instructions which were not present in AVX-512BW. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「AVX-512」の詳細全文を読む スポンサード リンク
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