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ARM big.LITTLE
ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively slower, low-power processor cores (''LITTLE'') with relatively more powerful and power-hungry ones (''big''). Typically, only one "side" or the other will be active at once, but since all cores have access to the same memory areas, workload can be swapped from big to LITTLE and back on the fly. The intention is to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone. ARM's marketing material promises up to a 75% savings in power usage for some activities.
In October 2011, big.LITTLE was announced along with the Cortex-A7, which was designed to be architecturally compatible with the Cortex-A15.〔 In October 2012 ARM announced the Cortex-A53 and Cortex-A57 (ARMv8-A) cores, which are also compatible with each other to allow their use in a big.LITTLE chip.〔 ARM later announced the Cortex-A12 at Computex 2013 followed by the Cortex-A17 in February 2014, both can also be paired in a big.LITTLE configuration with the Cortex-A7.〔(【引用サイトリンク】title=ARM's new Cortex-A12 is ready to power 2014's $200 midrange smartphones )〕〔(【引用サイトリンク】title=ARM Cortex A17: An Evolved Cortex A12 for the Mainstream in 2015 )〕
== Run-state migration==
There are three ways for the different processor cores to be arranged in a big.LITTLE design, depending on the scheduler implemented in the kernel.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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