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In computer science, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past, channels were generally implemented with custom processors, variously named channel, peripheral processor, I/O processor, I/O controller, or DMA controller. == Overview == Many I/O tasks can be complex and require logic to be applied to the data to convert formats and other similar duties. In these situations, the simplest solution is to ask the CPU to handle the logic, but because I/O devices are relatively slow, a CPU could waste time (in computer perspective) waiting for the data from the device. This situation is called 'I/O bound'. Channel architecture avoids this problem by using a separate, independent, low-cost processor. Channel processors are simple, but self-contained, with minimal logic and sufficient on-board scratchpad memory (working storage) to handle I/O tasks. They are typically not powerful or flexible enough to be used as a computer on their own and can be construed as a form of coprocessor. A CPU sends relatively small channel programs to the controller via the channel to handle I/O tasks, which the channel and controller can, in many cases, complete without further intervention from the CPU (exception: those channel programs which utilize 'program controlled interrupts', PCIs, to facilitate program loading, demand paging and other essential system tasks). When I/O transfer is complete or an error is detected, the controller communicates with the CPU through the channel using an interrupt. Since the channel has direct access to the main memory, it is also often referred to as ''DMA controller'' (where DMA stands for direct memory access), although that term is looser in definition and is often applied to non-programmable devices as well. In the most recent implementations, the channel program is initiated and the channel processor performs ''all'' required processing until either a "success" or a "failure" result occurs. This eliminates much of the CPU—Channel interaction and greatly improves overall system performance. If a "success" is posted to the CPU, the result is obvious: the channel program had run to completion and no errors or exceptions were encountered. If a "failure" is posted to the CPU, the result is less obvious—surely an error or exception of some kind was encountered, and the channel program was incomplete, but enough diagnostic information is provided from the channel processor to the CPU so that the channel program may be restarted with a minimum of overhead. In earlier implementations, ''any'' error, no matter how small, required CPU intervention, and the overhead was, consequently, much higher. A program-controlled interruption (PCI) is still supported for certain "legacy" operations, but the trend is to move away from such PCIs, except where unavoidable. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Channel I/O」の詳細全文を読む スポンサード リンク
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