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Elbrus-2S+
Elbrus-2S+ ((ロシア語:Эльбрус-2С+)) is a multi-core microprocessor based on the Elbrus 2000 architecture developed by Moscow Center of SPARC Technologies (MCST) 〔〔〔 There are multiple reports regarding the evolution of this technology for the purpose of import substitution in Russia, which was raised by several ministries on July, 2014 due to economic sanctions in response to 2014 pro-Russian unrest in Ukraine.〔〔〔〔 In December 2014, it was announced that Mikron start pilot production of a dual-core variant of this microprocessor called Elbrus-2SM ((ロシア語:Эльбрус-2СM)) using a 90 nanometer CMOS manufacturing process in Zelenograd, Russia.〔〔〔〔〔
==Technology==
The Elbrus-4S CPU is reported to have built in support for Intel x86 emulation as well as a native VLIW mode where it can perform up to 23 instructions per clock cycle.〔〔〔
When programs are built for Elbrus 2000 native mode, the compiler determines how the different operations shall be distributed over the 23 computing units before saving the final program. This means that no dynamic scheduling is needed during runtime, thus reducing the amount of work the CPU has to perform every time program in executed. Because static scheduling only needs to be performed one time when the program is built, more advanced algorithms for finding the optimal distribution of work can be employed.〔〔
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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