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FJG RAM, short for ''Floating Junction Gate Random refers to feature size) and a capacitorless cell configuration. It is made without exotic process steps, materials or new process tools, and the process for making the device is available from all existing DRAM fabs. Due to the absence of a capacitor, the FJG cell process is more compatible with logic process, allowing its use not only in standalone DRAM applications but also in embedded-DRAM applications. Other properties include non-destructive-read and the possibility for DRAM designers to use shared sense-amplifiers to reduce the complexity of periphery circuits. == Device configuration and operation == Device Structure Fig.1 and Fig.2 show simulated structure picture and the equivalent circuit schematic of the FJG device, respectively. An FJG device consists of following parts as shown in Fig.1: #Source Region #Drain Region #Control Gate #Quasi-Floating Gate #Substrate #pn Diode Basic Operation As shown in Fig.2, the FJG device generally consists of one floating gate NMOS and one MOS gated diode. The floating gate NMOS has different threshold voltages at different logic states. By charging or discharging the floating gate via the current path through the gated diode, the threshold voltage of the floating gate NMOS is changed. Since the floating gate is connected to a p-n junction, this cell is called a "floating junction gate (FJG)" cell. When reading the cell, with the same voltage conditions on the control gate, the NMOS has different sense current at different logic states. The sense current can then be amplified by a sense amplifier. Thus, the state of the cell can be determined. Electrical Characteristic ''Program and Read Operations'' Writing logic "1" and "0" is done by charging and discharging the floating gate in an FJG cell. It is done through current flowing through the pn diode under different voltage stress conditions at different contact nodes. When charging the floating gate, the pn diode is reverse biased, causing large band bending at the floating gate/channel junction. Band-to-Band tunneling will occur under such condition causing electrons tunnel from the floating gate to the channel''(Fig.3(a))''. Discharging the floating gate is realized by forward biasing the pn diode and draining the charges out of the floating gate''(Fig.3(b))''. Both processes can be done within a few nano seconds, which enables ultra high speed operation. Fig. 4 illustrates the transient characterization of the read and write operations of an FJG device, wherein the write logic "1" and "0" operations take 5 ns including 1ns rising/falling edge of the signal pulse. It can be seen that the read logic "1" current is as high as 20μA after the write logic "1" operation while the read logic "0" current is less than 1μA after the write "0" operation. The write "1" operation can be even faster with an increased VD-S. Non-destructive read: Fig.5 shows the dependence of a delta-shaped Vfg on the read time; the delta Vfg represents the difference in Vfg between identical memory cells in “1” versus “0” states. It can be seen that the read-operation of the FJG cell is quasi non-destructive. The non-destructive read operation endurance can be longer than 1 ms at Vcg=1.6 V. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「FJG」の詳細全文を読む スポンサード リンク
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