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GAL22V10
The GAL22V10 is a series of programmable-logic devices implemented as CMOS-based generic array logic ICs, created by Lattice Semiconductor, and available as a Dual inline package or a Plastic leaded chip carrier. While it is an example of a standard production GAL device it is often used in educational settings as a basic PLD.〔〔〔
== Specifications ==
The GAL22V10 has 12 input pins, and 10 pins that can be configured as either inputs or outputs, and exists in various switching speeds, from 25 to 4 ns. Each output is driven by an output-logic macrocell, with an output-enable product term, and a variable number of product terms, ranging from eight to sixteen. Each OLMC may be set to output as inverting or non-inverting, and be placed into either registered or combinatorial mode. In registered mode, each macrocell actively uses a D-flip-flop to hold a state under control of the data input from the logic portion of the macrocell and the rising edge of the clock signal, while in combinatorial mode the flip-flop is removed from the macrocell and the outputs are driven directly by the logic. In the latter mode, the pin may also dynamically switch between input and output based on the product term. In either mode the pin value is fed back into the array as a product term. Combinations are set using an E2PROM The output registers can be preloaded into a potentially invalid state for testing by a GAL22V10 programmer. Inputs and outputs include active pull-ups and are transistor-transistor logic compatible due to high-impedance buffers.〔(【引用サイトリンク】url=http://web.mit.edu/6.115/www/datasheets/GAL22V10.pdf )〕
A user electronic signature section is included for details such as user ID codes, revision IDs, or asset tagging on official Lattice Semiconductor units, as well as a static ES section for compatibility with non-Lattice Semiconductor GAL22V10 units. In addition, a security cell is included which, when set, disallows the retrieval of the array logic from the chip, until a new set of logic is set.
Latch-up protection is implemented using n-pullups and a charge pump in the official Lattice Semiconductor models.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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