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The following is a ''partial'' list of Intel CPU microarchitectures. The list is ''incomplete''. == x86 microarchitectures == * 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. * 186: included a DMA controller, interrupt controller, timers, and chip select logic. * 286: first x86 processor with protected mode * i386: first 32-bit x86 processor * i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. * P5: original Pentium microprocessors * P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. * * Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing. * * Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in Core microprocessors. * NetBurst: used in Pentium 4, Pentium D, and some Xeon microprocessors. Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Later revisions were the first to feature Intel's x86-64 architecture. * Core: reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process. * * Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, and SSE4.1 instructions. * Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. * * Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features. * Sandy Bridge: released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.〔(【引用サイトリンク】 title=An Update On Our Graphics-related Programs )〕 * * Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012. * Haswell: 22 nm microarchitecture, released June 3, 2013. * * Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell. * Skylake: new 14 nm microarchitecture, released August 5, 2015. * * Kaby Lake: expected in 2016, breaking Intel's Tick-Tock schedule due to delays with the 10 nm process. * * Cannonlake: 10 nm shrink of Kaby Lake. Formerly called Skymont. * Larrabee: multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core). * Bonnell: 45 nm, low-power, in-order microarchitecture for use in Atom processors. * * Saltwell: 32 nm shrink of the Bonnell microarchitecture. * Silvermont: 22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013. * * Airmont: 14 nm shrink of the Silvermont microarchitecture. * Goldmont: 14 nm Atom microarchitecture. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「List of Intel CPU microarchitectures」の詳細全文を読む スポンサード リンク
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