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M·CORE
M·CORE is a low-power, RISC-based microcontroller architecture developed by Motorola (now Freescale), intended for use in embedded systems. Introduced in late 1997, the architecture combines a 32-bit internal data path with 16-bit instructions,〔(microRISC Engine, Programmers Reference Manual, Revision 1.0 )〕 and includes a four-stage instruction pipeline. Initial implementations used a 0.36 micrometre process and ran at 50 MHz.
M·CORE processors〔(MCore2114, 2113, 2112, Advanced Information )〕 employ a Princeton architecture with shared program and data bus—executing instructions from within data memory is possible. Motorola engineers designed M·CORE to have low power consumption and high code density.〔
(M•CORE Architectural Brief ).
1997.
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抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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