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NanGate, Inc is a privately held US/Silicon Valley-based multinational corporation dealing in Electronic Design Automation (EDA) for electrical engineering and electronics. NanGate was founded in October 2004 by a group of semiconductor professionals with a background from Intel Corporation and Vitesse Semiconductor Corp. The company has received capital investments from a group of Danish business angels and venture capital companies. The company is today owned and controlled by its management following a management buy-out in 2012. NanGate markets a range of software products and design services for the design and optimization of standard cell libraries and application-specific integrated circuits. The market focus is standard cell library design and optimization for 14-28 nanometer CMOS processes. ==History== NanGate was founded in October 2004 by a group of semiconductor professionals from Vitesse Semiconductor Corp. Prior to Vitesse, the team had founded Exbit Technology, a fabless semiconductor start-up focused on the market for Gigabit and 10 Gigabit Ethernet ASSPs used in high performance data- and telecommunications switching and routing equipment. Exbit Technology was acquired by Vitesse Semiconductor Corp in 2001. The technology and market idea behind the foundation of NanGate was to address and solve the inherent shortcomings of standard cell based ASSP/ASIC design as compared to full custom IC design. In standard cell design the designer uses cells from a standard cell library to implement the desired logic functionality of the IC while trying to obtain the target operating frequency at the lowest possible cost in terms of die area and power consumption. The standard cells form the basic building blocks used to build the IC together with macro blocks such as embedded memory, Input-Output (IO), mixed-signal and analog blocks. Each standard cell represents a relatively primitive logic function, such as a NAND gate, with fixed area, timing and power characteristics and is constructed from transistors most often arranged in the pull-up/pull-down fashion of CMOS. A typical standard-cell library for e.g. 40 nanometer CMOS has 500-1500 standard cells and about 150-300 different logic functions. The benefits of the standard cell library design methodology are many but compared to full-custom IC design there is a large gap between what can be achieved when comparing the two methodologies in terms of highest possible operating frequency, lowest possible die area and power consumption. This is first and foremost due to the fact that in full-custom IC design, the engineer can handcraft and optimize the design on the transistor level without having to use only fixed-sized standard cells. Full-custom IC design is much more resource and time-consuming and only a minority of ICs have a market potential that is able to pay for such an investment in research and development. NanGate addresses this gap by providing the IC designer with a range of software products that allow him to specify and create new standard cells with custom transistor layout in an automated manner. The IC designer can thereby augment and optimize the cell library used to implement the IC. This process of growing and tweaking the cell library enables higher performance, lower die area and lower power consumption which serve to narrow the gap between the standard-cell and full-custom design methodologies. This patent-protected technology is core to NanGate's range of software products. During 2004-2006, the NanGate team worked on developing a library creation platform with built-in automation for layout creation and library characterization (the process of SPICE simulating the extracted circuit netlist with parasitics and building a model used for static timing analysis). This resulted in two software products, NanGate Library Creator(TM) and Nangate Library Characterizer(TM), the prototype versions of which were introduced at the annual Design Automation Conference in 2005 and the first official releases of the two products the following year, DAC-2006. Nangate Library Characterizer(TM) got on John Cooley’s best-of-DAC 2006 list. In October 2005, NanGate established collaboration with UFRGS (a university located in Porto Alegre, Brazil) that resulted in NanGate Labs, and later in 2006 the establishment of NanGate do Brasil SA, a research and development subsidiary in the same location. The Brazilian based subsidiary was closed down in 2011 in order to consolidate the R&D teams in fewer locations. In 2006, NanGate received USD $10 million in venture capital investment from 3 Danish-based venture capital companies: Vækstfonden, IVS and SeeD Capital. Also in 2006, NanGate, Inc was established in Sunnyvale, CA, USA in order to promote sales and support customers in the Silicon Valley area. The company also established a subsidiary in Moscow, the Russian Federation to focus on research and development in layout compaction technologies. This subsidiary was closed in the fall of 2012. NanGate was awarded the Ernst and Young "Entrepreneur of the Year 2007" in the start-up category in the Danish region. Also in 2007, NanGate released two new software products, NanGate Liberty Analyze(TM) and NanGate Design Audit(TM). The software products target the verification and cross-check of the library characterization. In 2008, NanGate introduced the first prototype version of NanGate Design Optimizer(TM) at the Design Automation Conference. Also, in 2008, NanGate donated a free 45 nm open source digital library through Si2 to promote interoperability and independent testing of standard cell based software products. The open cell library is one of the most used libraries for independent EDA flow testing and academic research. It can be downloaded from the website of Si2 and was updated in 2011. In 2009, NanGate was awarded the "Best Presentation Award" at the Nordic Venture Summit 2009. Also in 2009, the company released the first so-called MegaLibrary(TM) for 65 nm SoC design. A MegaLibrary is a very large standard cell library in terms of logic functions and variants in terms of drive strength and relative transistor sizing (such as P/N ratio or tapered inputs). A pre-made MegaLibrary presents an alternative to creating new standard cells on-the-fly (e.g. using NanGate Library Creator) for optimization purposes. As a typical standard cell library contains only a small subset of the possible Boolean functions, 2 or more standard cells are needed to implement functions not found in the library. As an example, there are 3984 Boolean P-equivalent functions with 4 inputs and about 37 million with 5 inputs.〔(【引用サイトリンク】title=Classifying n-input Boolean functions )〕 The concept of automatic generation of footprint-compatible cells was also introduced. A set of standard cells are said to be footprint compatible when they are interchangeable from a place-and-route perspective without causing DRC errors. Footprint-compatibility is typically obtained from a maximum sized base cell from which versions are derived having identical layers from metal-1 and up but having differently sized diffusion areas to implement transistor sizing variants. The combination of NanGate MegaLibrary(TM) and NanGate Design Optimizer(TM) enables a new type of digital gate-level re-synthesis where the library and library content becomes part of the optimization objective. During optimization, subsets of library cells are selected and presented to the technology mapper while other subsets are forcefully removed from the set of allowed cells. In this manner, the optimal library subset from the MegaLibrary is selected for the particular digital design block being optimized. A MegaLibrary with a large set of footprint-compatible cells can be used for timing and power optimization after the place-and-route stage is completed. During 2009-2011, NanGate continued development on the Library Platform products and Nangate Design Optimizer(TM) and released updated versions targeting more and more advanced process nodes leading to support for 28 nm in 2009 and 22 nm in 2011 with public announcements from two customers, TSMC and Fujitsu. In 2010, NanGate was appointed to lead the European SYNAPTIC project, a project to define next-generation design methodologies with focus on methods to enhance lithography-based yield. The SYNAPTIC project, now completed, was done in collaboration with STMicroelectronics, IMEC, Politecnico di Milano (Italy), Universitat Politècnica de Catalunya (Spain) and Universidade Federal do Rio Grande do Sul (Brazil) In 2012, the company went through a restructure process and changed ownership as three of the original founders completed a management buy-out. The Danish legal entity NanGate A/S went through a bankruptcy process as the venture capital owners of NanGate A/S decided not to provide additional capital. As part of the restructure process NanGate, Inc became the new headquarter, located in Silicon Valley. A new Danish legal entity was established to replace and take over research and development activities from NanGate A/S. In 2013, NanGate announced a strategic collaboration with Sagantec to provide library design capability for 14-22 nm process technologies. Process technologies at geometries below 28 nm present new technological challenges that affect the transistor layout and metal layers used in the standard cells. Usage of next-generation lithography technologies such as double-patterning and coloring are new methods that enables scaling to 14 nm geometries. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「NanGate」の詳細全文を読む スポンサード リンク
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