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OpenRISC is a project to develop a series is an open source instruction set architectures based on established reduced instruction set computing (RISC) principles. It is the original flagship project of the OpenCores community The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support,〔Damjan Lampret et al., "OpenRISC 1000 Architecture Manual", Architecture Version 1.0, Document Revision 0, December 5, 2012. Available from the OpenCores website ()〕 and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language.〔Interview with OpenRISC designer Damjan Lampret, published online in EE Times in February 2000 ()〕〔Interview with OpenRISC designer Damjan Lampret, on the cover of February 2000 edition of EE Times()〕 The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL). A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups have demonstrated ORPSoC and other OR1200 based designs running on FPGAs,〔Patrick Pelgrims, Tom Tierens and Dries Driessens, "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGA’s", De Nayer Instituut, Hogeschool voor Wetenschap & Kunst, 2004. Available online ()〕〔Xiang Li and Lin Zuo, "Open source embedded platform based on OpenRISC and DE2-70", Masters dissertation, SoC program, KTH, Sweden. Available online ()〕 and there have been a number of commercial derivatives produced. == Instruction set == The instruction set is a reasonably simple MIPS-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32 and 64 bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop/server processors: a supervisor mode and virtual memory system, optional read, write and execute control for memory pages, and instructions for synchronization and interrupt handling between multiple processors. Another notable feature is a rich set of SIMD instructions intended for digital signal processing. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「OpenRISC」の詳細全文を読む スポンサード リンク
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