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RISC-V (pronounced "risk-five") is an open source instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles. In contrast to most ISAs, RISC-V is freely available for all types of use, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, which fixes the usual weakness of new instruction sets. The project was originated in 2010 by researchers in the Computer Science Division at UC Berkeley, but many contributors are volunteers and industry workers that are unaffiliated with the university.〔 The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind,〔〔 but without "over-architecting" for a particular microarchitecture style.〔〔 As of 2014 version 2 of the userspace ISA is fixed.〔 == Significance == The RISC-V authors aim to provide several freely available CPU designs, under a BSD license. This license allows derivative works such as RISC-V chip designs to be either open and free like RISC-V itself, ''or'' closed and proprietary, (unlike the available OpenRISC cores, which under the GPL, requires that all derivative works also be open and free). By contrast, commercial chip vendors such as ARM Holdings and MIPS Technologies charge substantial license fees for the use of their patents.〔Demerjian, C. (2013). “A long look at how ARM licenses chips: Part 1” semiaccurate.com/2013/08/07/a-long-look-at-how-arm-licenses-chips, “How ARM licenses it’s IP for production: Part 2” semiaccurate.com/2013/08/08/how-arm-licenses-its-ip-for-production〕 They also require non-disclosure agreements before releasing documents that describe their designs' advantages and instruction set. Many design advances are completely proprietary, never described even to customers. The secrecy interferes with legitimate public educational use, security auditing, and the development of public, inexpensive open-source free software compilers and operating systems. Developing a CPU requires expertise in several specialties: Logic design, compiler design and operating system design. It's rare to find this outside of a professional engineering team. The result is that modern, high-quality general-purpose computer instruction sets have not recently been widely available anywhere or even explained except in academic settings. Because of this, many RISC-V contributors see it as a unified community effort. This need for a large base of contributors is part of the reason why RISC-V was engineered to fit so many uses. The RISC-V authors also have substantial research and user-experience validating their designs in silicon and simulation. The RISC-V ISA is a direct development from a series of academic computer-design projects and was originated in part to aid such projects.〔〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「RISC-V」の詳細全文を読む スポンサード リンク
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