|
The RapidIO architecture is a high-performance packet-switched, interconnect technology. RapidIO supports messaging, read/write and cache coherency semantics. RapidIO fabrics guarantee in-order packet delivery, enabling power- and area- efficient protocol implementation in hardware. Based on industry-standard electrical specifications such as those for Ethernet, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect. The protocol is marketed as: ''RapidIO - the unified fabric for Performance Critical Computing'',〔http://www.rapidio.org〕 and is used in many applications such as Data Center & HPC, Communications Infrastructure, Industrial Automation and Military & Aerospace that are constrained by at least one of size, weight, and power (SWaP). == History == RapidIO has its roots in energy-efficient, high-performance computing. The protocol was originally designed by Mercury Computer Systems and Motorola (Freescale) as a replacement for Mercury’s RACEway proprietary bus and Freescale's PowerPC bus. The RapidIO Trade Association was formed in February 2000, and included telecommunications and storage OEMs as well as FPGA, processor, and switch companies. The protocol was designed to meet the following objectives: * Low latency * Guaranteed, in order, packet delivery * Support for messaging and read/write semantics * Could be used in systems with fault tolerance/high availability requirements * Flow control mechanisms to manage short-term (less than 10 microseconds), medium-term (tens of microseconds) and long-term (hundreds of microseconds to milliseconds) congestion * Efficient protocol implementation in hardware * Low system power * Scales from two to thousands of nodes The RapidIO Specification Revision 1.1, released in 2001, defined a wide, parallel bus. This specification did not achieve extensive commercial adoption. The RapidIO Specification Revision 1.2, released in 2002, defined a serial interconnect based on the XAUI physical layer. Devices based on this specification achieved significant commercial success within wireless baseband, imaging and military compute. The RapidIO Specification Revision 2.0, released in 2008, added more port widths (2×, 8×, and 16×) and increased the maximum lane speed to 6.25 Gbd (gigabaud). Revision 2.1 has repeated and expanded the commercial success of the 1.2 specification. The RapidIO Specification Revision 3.0, released in 2013, has the following changes and improvements compared to the 2.x specifications: * Based on industry-standard Ethernet 10GBASE-KR electrical specifications for short (20 cm + connector) and long (1 m + 2 connector) reach applications * Directly leverages the Ethernet 10GBASE-KR DME training scheme for long-reach signal quality optimization * Defines a 64b/67b encoding scheme (similar to the Interlaken standard) to support both copper and optical interconnects and to improve bandwidth efficiency * Dynamic asymmetric links to save power (for example, 4× in one direction, 1× in the other) * Addition of a time synchronization capability similar to IEEE 1588, but much less expensive to implement * Support for 32-bit device IDs, increasing maximum system size and enabling innovative hardware virtualization support * Revised routing table programming model simplifies network management software * Packet exchange protocol optimizations 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「RapidIO」の詳細全文を読む スポンサード リンク
|