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SSE4
SSE4 (Streaming SIMD Extensions 4) is a CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on 27 September 2006 at the Fall 2006 Intel Developer Forum, with vague details in a white paper;〔(Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation ), Intel.〕 more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation.〔(Tuning for Intel SSE4 for the 45nm Next Generation Intel Core Microarchitecture ), Intel.〕 SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4.〔(Intel SSE4 Programming Reference )〕 The (SSE4 Programming Reference ) is available from Intel.
==SSE4 subsets==
Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as ''SSE4.1'' in some Intel documentation, is available in Penryn. Additionally, ''SSE4.2'', a second subset consisting of the 7 remaining instructions, is first available in Nehalem-based Core i7. Intel credits feedback from developers as playing an important role in the development of the instruction set.
Starting with Barcelona-based processors, AMD introduced the ''SSE4a'' instruction set, which has 4 SSE4 instructions and 4 new SSE instructions. These instructions are not found in Intel's processors supporting SSE4.1 and AMD processors only started supporting Intel's SSE4.1 and SSE4.2 (the full SSE4 instruction set) in the Bulldozer-based FX processors. With SSE4a the misaligned SSE feature was also introduced which meant unaligned load instructions were as fast as aligned versions on aligned addresses. It also allowed disabling the alignment check on non-load SSE operations accessing memory.〔(【引用サイトリンク】url=http://developer.amd.com/community/blog/2008/04/14/barcelona-processor-feature-sse-misaligned-access/ )〕 Intel later introduced similar speed improvements to unaligned SSE in their Nehalem processors, but did not introduce misaligned access by non-load SSE instructions until AVX.〔(【引用サイトリンク】url=http://www.hardwaresecrets.com/article/Inside-Intel-Nehalem-Microarchitecture/535/7 )〕
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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