翻訳と辞書 Words near each other ・ Swarnandhra College of Engineering and Technology ・ Swarnandhra Pradesh Sports Complex ・ Swarnapitha ・ Swarnappakshikal ・ Swarnapureeswarar Temple, Sembanarkoil ・ Swarnarekha express ・ Swarnavahini ・ Swarnavigraham ・ Swarndih ・ Swarnim Wagle ・ Swarnkar ・ Swaps (horse) ・ Swaps Regulatory Improvement Act ・ SwapSimple ・ Swaption ・ SWAR ・ Swar Khan ・ Swar Sagar- The School of Music ・ Swar Utsav ・ Swara ・ Swara (custom) ・ Swara (Indonesia) ・ Swara Bhaskar ・ Swara Magazine ・ Swara Samrat festival ・ Swara, Nepal ・ Swarabat ・ Swarabhishekam ・ Swarachakra ・ Swarag Se Sunder Dictionary Lists mini英和辞書 mini和英辞書 Webster 1913 Latin-English FOLDOC Wikipedia English ウィキペディア

翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク SWAR ： ウィキペディア英語版 SWAR SIMD within a register (SWAR) is a technique for performing parallel operations on data contained in a processor register. SIMD stands for ''single instruction, multiple data''. Many modern general-purpose computer processors have some provisions for SIMD, in the form of a group of registers and instructions to make use of them. SWAR refers to the use of those registers and instructions, as opposed to using specialized processing engines designed to be better at SIMD operations. It also refers to the use of SIMD with general-purpose registers and instructions that were not meant to do it at the time, by way of various novel software tricks. ==SWAR architectures== A SWAR architecture is one which includes instructions explicitly intended to perform parallel operations across data that is stored in the independent subwords or fields of a register. A SWAR-capable architecture is one which includes a set of instructions that is sufficient to allow data stored in these fields to be treated independently even though the architecture does not include instructions that are explicitly intended for that purpose. An early example of a SWAR architecture was the Intel Pentium with MMX, which implemented the MMX extension set. The Intel Pentium, by contrast, did not include such instructions, but could still act as a SWAR architecture through careful hand-coding or compiler techniques. Early SWAR architectures include Digital Equipment Corporation's Alpha processor, Hewlett-Packard's PA-RISC, Silicon Graphics Incorporated's MIPS, and Sun's SPARC V9.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「SWAR」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.