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Incisive Enterprise Specman® Elite Testbench (abbreviated simply as Specman) is a tool that automates certain steps of the semiconductor design and verification process and provides for functional coverage analysis at the architectural/specification level. It is part of the Cadence® Incisive® functional verification platform. Specman is an EDA tool that provides advanced automated Functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the ''e'' Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification. == Introduction to Specman == The Specman Elite system provides three main enabling technologies intended to improve productivity: * Constraint-driven test generation—Users control automatic test generation by capturing constraints from the interface specifications and the functional test plan. * Data and temporal checking— Users create self-checking modules that ensure data correctness and temporal conformance. For data checking, reference model or rule-based approaches can be used. * Functional coverage analysis— Users can measure the progress of verification efforts against a functional test plan. The Specman tool itself does not include an HDL-simulation environment (such as VHDL or Verilog.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. In principle, Specman can co-simulate with any HDL-simulator supporting standard PLI or VHPI interface, such as Cadence's Incisive Enterprise Simulator (formerly known as NCSim), NC-Sim or Verilog-XL, Synopsys's (VCS ), or Mentor's Questa (formerly known as ModelSim)(ModelSim ), or Aldec's Riviera-PRO. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Specman」の詳細全文を読む スポンサード リンク
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