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The TMS320C4x is the second generation of 32-bit floating point digital signal processors. The first family member, the TMS320C40, was introduced in 1990. TMS320C4x family members target multiprocessor floating-point DSP systems for scientific, industrial, and military applications. The TMS320C4x is similar to (and object-code compatible with) its predecessor, TMS320C3x. ==Key features of the TMS320C4x== The TMS320C4x has several key features: * IEEE floating-point conversion for ease of use * Register-based CPU * Single-cycle byte and half-word manipulation capabilities * Divide and square root support for improved performance * On-chip memory includes 2K words of SRAM, 128 words of program cache, and boot loader * Two external buses providing an address reach of up to 4 gigawords * Two memory-mapped 32-bit timers * 6 and 12 channel DMA * Up to six communication ports for multiprocessor communication * Idle mode for reduced power consumption 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「TMS320C4x」の詳細全文を読む スポンサード リンク
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