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The VIDC20 was a Video Display Controller chip created as an accompanying chip to the ARM CPU as used in RiscPC computer systems. 〔(description of RiscPC hardware )〕〔(VIDC20 datasheet )〕 A simpler version of the VIDC20 the VIDC1 was used in the earlier Acorn Archimedes computers. A VIDC20 chip controls both the computer’s video and sound. The data is read from the 64-bit ARM data bus using DMA control and then processed and converted into the necessary analogue signals to drive the video output displays and sound system. The VIDC20 can handle many more display and sound formats than the original VIDC1 chip found in the Archimedes Hardware. It can also read data from VRAM if installed in the machine, otherwise it reads from DRAM. ==Video== Data from the video buffer is converted and processed, as follows: Data is serialised by the VIDC20 chip into either 1, 2, 4, 8, 16 or 32 bits per pixel, then passed through a colour look-up palette RAM. The palette has 256 28-bits wide registers; 8 Red bits, 8 Green bits, 8 Blue bits and 4 bits for external data) The output is then converted by three 8-bit DACs. One each for red, green and blue colour. Output is then used to drive the display output device with a maximum of 16 million possible colours. The VIDC20 chip can handle any pixel rate up to 110 MHz. With the clock selected from one of three sources, which can then be further divided by a factor between 1 and 8. In addition it also contains a phase comparator which allows for a single clock to generate all the required frequencies for any display mode. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「VIDC20」の詳細全文を読む スポンサード リンク
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