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A wide-issue architecture is a computer processor that issues more than one instruction per clock cycle. They can be considered in three broad types: * Statically-scheduled superscalar architectures execute instructions in the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle. * VLIW architectures rely on the programming software (compiler) to determine which instructions to dispatch on a given clock cycle. * Dynamically-scheduled superscalar architectures execute instructions in an order that gives the same result as the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.〔(【引用サイトリンク】first1=Milo )〕 ==See also== *Out-of-order execution *Explicitly parallel instruction computing 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Wide-issue」の詳細全文を読む スポンサード リンク
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