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XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE). XAUI is pronounced "zowie", a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface". The XGMII Extender, which is composed of an XGXS (XGMII Extender Sublayer) at the MAC end, an XGXS at the PHY end and a XAUI between them, is to extend the operational distance of the XGMII and to reduce the number of interface signals. Applications include extending the physical separation possible between MAC and PHY components in a 10 Gigabit Ethernet system distributed across a circuit board. ==Operation== XGMII Extender has the following characteristics: * Simple signal mapping to the XGMII * Independent transmit and receive data paths * Four lanes conveying the XGMII 32-bit data and control * Differential signaling with low voltage swing (1600 mVp-p) * Self-timed interface allows jitter control to the PCS * Shared technology with other 10 Gbit/s interfaces * Shared functionality with other 10 Gbit/s Ethernet blocks * Utilization of 8b/10b encoding The following is a list of the major concepts of XGXS and XAUI: * The optional XGMII Extender can be inserted between the Reconciliation Sublayer and the PHY (physical layer) to transparently extend the physical reach of the XGMII and reduce the interface pin count from 72 to 16. * The XGMII is organized into four lanes with each lane conveying a data octet or control character on each edge of the associated clock. The source XGXS converts bytes on an XGMII lane into a self clocked, serial, 8b/10b encoded data stream. Each of the four XGMII lanes is transmitted across one of the four XAUI lanes. * The source XGXS converts XGMII Idle control characters (interframe) into an 8b/10b code sequence. The destination XGXS recovers clock and data from each XAUI lane and deskews the four XAUI lanes into the single-clock XGMII. * The destination XGXS adds to or deletes from the interframe as needed for clock rate disparity compensation prior to converting the interframe code sequence back into XGMII Idle control characters. * The XGXS uses the same code and coding rules as the 10GBASE-X PCS and PMA specified in Clause 48 of the IEEE 802.3 Specification. * Each of the 4 Receive and Transmit lanes operates at a rate of 3.125 Gbit/s. * Capabilities have been built into XAUI to overcome the inter-lane signal-skewing problems using a type of automatic de-skewing. Signals can be launched at the transmitter end of a XAUI line without precisely matching the routing of the four lanes, and the signals will be automatically de-skewed at the receiver. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「XAUI」の詳細全文を読む スポンサード リンク
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