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Microsoft XCPU, codenamed Xenon, is a CPU used in the Xbox 360 game console, to be used with ATI's Xenos graphics chip. The processor was developed by Microsoft and IBM under the IBM chip program codenamed "Waternoose", which was named after Henry J. Waternoose III in ''Monsters, Inc.''.〔("Learning from failure - The inside story on how IBM out-foxed Intel with the Xbox 360" ), Dean Takahashi, ''Electronic Business'', May 1, 2006〕 The development program was originally announced on 2003-11-03.〔(【引用サイトリンク】title=IBM News room - 2003-11-03 Microsoft and IBM Announce Technology Agreement - United States )〕 The processor is based on IBM PowerPC instruction set architecture. It consists of three independent processor cores on a single die. These cores are slightly modified versions of the PPE in the Cell processor used on the PlayStation 3.〔"(Processing The Truth: An Interview With David Shippy )", Leigh Alexander, ''Gamasutra'', January 16, 2009〕〔"(Playing the Fool )", Jonathan V. Last, ''Wall Street Journal'', December 30, 2008〕 Each core has two symmetric hardware threads (SMT), for a total of six hardware threads available to games. Each individual core also includes 32 KiB of L1 instruction cache and 32 KiB of L1 data cache. The XCPU processors are manufactured at IBM's East Fishkill, New York fabrication plant and Chartered Semiconductor Manufacturing (now part of GlobalFoundries) in Singapore.〔(【引用サイトリンク】title=IBM News room - 2005-10-25 IBM Delivers Power-based Chip for Microsoft Xbox 360 Worldwide Launch - United States )〕 Chartered reduced the fabrication process in 2007 to 65 nm from 90 nm, thus reducing manufacturing costs for Microsoft. ==Specifications== *90 nm process, 65 nm process upgrade in 2007 (codenamed "Falcon", later "Jasper"), 45 nm process since Xbox 360 S model *165 million transistors *Three symmetrical cores, each two way SMT-capable and clocked at 3.2 GHz〔 *SIMD: 2xVMX128 with dedicated (128×128 bit) register file for each core,〔 one for each thread *1 MB L2 cache〔 (lockable by the GPU) running at half-speed (1.6 GHz) with a 256-bit bus *51.2 GB/s of L2 memory bandwidth (256 bit × 1600 MHz) *21.6 GB/s front-side bus (On the CPU side, this interfaces to a 1.35 GHz, 8B wide, FSB dataflow; on the GPU side, it connects to a 16B wide FSB dataflow running at 675Mhz.)〔 *Dot product performance: 9.6 billion per second *Restricted to in-order code execution〔 *eFuse 768 bits *ROM (and 64 KB SRAM) storing Microsoft's Secure Bootloader, and encryption hypervisor〔 *Big endian architecture 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Xenon (processor)」の詳細全文を読む スポンサード リンク
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