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In electronics, a subtractor can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit numbers, three bits are involved in performing the subtraction for each bit of the difference: the minuend (), subtrahend (), and a borrow in from the previous (less significant) bit order position (). The outputs are the difference bit () and borrow bit . The subtractor is best understood by considering that the subtrahend and both borrow bits have negative weights, whereas the X and D bits are positive. The operation performed by the subtractor is to rewrite (which can take the values -2, -1, 0, or 1) as the sum . : : Subtractors are usually implemented within a binary adder for only a small cost when using the standard two's complement notation, by providing an addition/subtraction selector to the carry-in and to invert the second operand. : (definition of two's complement negation) : ==Half subtractor== The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend and subtrahend and two outputs the difference and borrow out . The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, if and only if and . An important point worth mentioning is that the half subtractor diagram aside implements and not since on the diagram is given by :. This is an important distinction to make since subtraction itself is not commutative, but the difference bit is calculated using an XOR gate which is commutative. The truth table for the half subtractor is: Using the table above and a Karnaugh map, we find the following logic equations for and : : :. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「subtractor」の詳細全文を読む スポンサード リンク
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